Today's computer systems are becoming increasingly sophisticated, permitting users to perform an ever greater variety of computing tasks at faster and faster rates. The size of the memory and the speed at which it can be accessed bear heavily upon the overall speed of the computer system.
Generally, the principle underlying the storage of data in a magnetic media (main or mass storage) is the ability to change, and/or reverse, the relative orientation of the magnetization of a storage data bit (i.e. the logic state of a “0” or a “1”). The coercivity of a material is the level of demagnetizing force that must be applied to a magnetic particle to reduce and/or reverse the magnetization of the particle. Generally speaking, the smaller the magnetic particle the higher it's coercivity.
A prior art magnetic memory cell may be a tunneling magneto-resistance memory cell (TMR), a giant magneto-resistance memory cell (GMR), or a colossal magneto-resistance memory cell (CMR). These types of magnetic memory are commonly referred to as magnetic tunnel junction memory (MTJ). As shown in prior art FIG. 1A and 1B a magnetic tunnel junction memory 100 generally includes a data layer 101 (also called a storage layer or bit layer), a reference layer 103, and an intermediate layer 105 between the data layer 101 and the reference layer 103. The data layer 101, the reference layer 103, and the intermediate layer 105 can be made from one or more layers of material.
The data layer 101 is usually a layer of magnetic material that stores a bit of data as an orientation of magnetization M2 that may be altered in response to the application of an external magnetic field or fields. More specifically, the orientation of magnetization M2 of the data layer 101 representing the logic state can be rotated (switched) from a first orientation representing a logic state of “0” to a second orientation, representing a logic state of “1”, and/or vice versa.
The reference layer 103 is usually a layer of magnetic material in which an orientation of magnetization M1 is “pinned”, as in fixed, in a predetermined direction. Often several layers of magnetic material are required and function as one to effectuate a stable pinned reference layer 103. The direction is predetermined and established by microelectronic processing steps employed in the fabrication of the magnetic memory cell.
The data layer 101 and reference layer 103 may be thought of as stacked bar magnets, each long on the X axis 107 and short on the Y axis 109. The magnetization of each layer has a strong preference to align along the easy axis, generally the long X axis 107. The short Y axis 109 is the hard axis. As with traditional bar magnets, the data layer and reference layer each have magnetic poles, one at either end of the easy axis.
The lines of magnetic force that surround a bar magnet are three-dimensional and flow from the North to the South pole. FIG. 2A is a simplified side view illustration of a typical bar magnet 200, it's magnetic orientation M and the surrounding magnetic field also referred to as lines of force (represented by arrows 201). As is shown in FIGS. 2B and 2C, generally, like poles repel and unlike poles attract. When opposite poles of two bar magnets (203 and 203′) are brought together, the lines of force 201 join up and pull the magnets together as in FIG. 2B. When like poles of two bar magnets (205 and 205′) are brought together, the lines of force 201 push away from each other and the magnets repel each other as in FIG. 2C.
These forces are most pronounced at either pole. As a result when two bar magnets of substantially equal length are evenly stacked lengthwise, both poles either simultaneously attract or simultaneously repel as they are directly proximity to one another.
Typically, the logic state (a “0” or a “1”) of a magnetic memory cell depends on the relative orientations of magnetization in the data layer 101 and the reference layer 103. For example, when an electrical potential bias is applied across the data layer 101 and the reference layer 103 in a MTJ 100, electrons migrate between the data layer 101 and the reference layer 103 through the intermediate layer 105. The intermediate layer 105 is typically a thin dielectric layer commonly referred to as a tunnel barrier layer. The phenomena that cause the migration of electrons through the barrier layer may be referred to as quantum mechanical tunneling or spin tunneling.
Continuing with the model of an elemental bar magnets, the magnetization of the data layer 101 is free to rotate, but with a strong preference to align in either direction along the easy axis 107 of the data layer 101. The reference layer 103 likewise is aligned along the easy axis 107 of the reference layer 103, but is pinned in a fixed alignment. The logic state may be determined by measuring the resistance of the memory cell. For example, if the overall orientation of the magnetization in the data layer 101 is parallel to the pinned orientation of magnetization in the reference layer 103 the magnetic memory cell will be in a state of low resistance. If the overall orientation of the magnetization in the data layer 101 is anti-parallel (opposite) to the pinned orientation of magnetization in the reference layer 103 the magnetic memory cell will be in a state of high resistance.
As the data layer 101 and reference layer 103 are substantially equal in length, and as the physical ends of the data layer 101 and reference layer 103 are symmetrically aligned, the poles of each layer are also proximate to one another. When the magnetic fields M1 and M2 are anti-parallel, as in FIG. 1A, there exists a strong magnetic attraction between both ends as illustrated by joined field lines 111 and 113. When the magnetic fields M1 and M2 are parallel, as in FIG. 1B, the magnetic fields emanating from the poles repel one another, as illustrated by field lines 115 and 117. As the poles are pre-disposed to attract, there is a strong desire for both poles of the data layer 101 to rotate away from their matching pole in the reference layer 103, as represented by arrows 119. This symmetric set of forces operating upon both ends of the data layer 101 and reference layer 103 at substantially the same time may be described simplistically as “two-end involvement.”
Storing a binary one or zero in the data layer 101 may require the orientation of the data layer 101 to be rotated, an event that may force the like poles to align, a condition they will fight, or permit opposite poles to align, a condition they desire. In either case, both poles of the data layer 101 and the reference layer 103 are involved and must be coerced to accept the new orientation. While the attraction between the poles reduces the required field to shift the orientation into anti-parallel, the repulsion at both ends requires a greater field to shift the orientation into parallel.
In an ideal setting the orientation of the alterable magnetic field in the data layer 101 would be either parallel or anti-parallel with respect to the field of the reference layer 103. As the data layer 101 and the reference layer 103 are generally both made from ferromagnetic materials and are positioned in close permanent proximity to each other, the generally stronger reference layer 103 may affect the orientation of the data layer 101. More specifically, the magnetization of the reference layer 103 may generate a demagnetization field that extends from the reference layer 103 into the data layer 101.
The result of this demagnetization field from the reference layer 103 is an offset in the coercive switching field. This offset can result in asymmetry in the switching characteristics of the bit: the amount of switching field needed to switch the bit from parallel to anti-parallel state is different from the switching field needed to switch the bit from anti-parallel state to parallel state. To have reliable switching characteristics and to simplify the read/write circuitry, it is desirable to have this offset reduced to as near zero as possible.
The magneto-resistance ΔR/R may be described as akin to a signal-to-noise ratio S/N. A higher S/N results in a stronger signal that can be sensed to determine the state of the bit in the data layer 101. Thus, at least one disadvantage of a tunnel junction memory cell having a pinned reference layer 103 in close and fixed proximity to the data layer 101 is a potential reduction in the magneto-resistance ΔR/R resulting from the angular displacement.
To pin the reference layer 103 during manufacturing, the reference layer 103 must be heated to an elevated temperature in an annealing step. The annealing step typically takes time, perhaps an hour or more. As the reference layer 103 is but one part of the memory being produced, the entire memory must be subject to temperatures ranging from about 200 to 300 degrees centigrade while under the influence of a constant and focused magnetic field. Such manufacturing stresses may permit the reference layer 103 to become un-pinned and lose it's set orientation if the memory is later subjected to high temperatures. In addition, the characteristics of the data layer 101 may be unknowingly affected by heat during some manufacturing processes.
To facilitate establishing a pinned reference layer 103 it is not uncommon for the reference layer 103 to include multiple layers of material. While utilizing multiple layers may help ensure that the reference layer 103 remains pinned, it also raises the complexity of manufacturing each and every memory cell present in the magnetic memory.
Main memory devices such as MRAM often employ tunnel junction magnetic memory cells positioned at the transverse intersections of electrically conductive rows and columns. Such an arrangement is known as a cross-point memory array.
In a typical cross-point memory array, while any given row (row A, B, C . . . ) may cross every column (column 1, 2, 3 . . . ), and visa-versa, the traditional principles of column and row arrays dictate that any given row will only cross any given column once. Therefore, by accessing a particular row (B) and a particular column (3), any one memory cell positioned at their intersection (B,3) can be isolated from any other memory cell in the array. Such individual indexing is not without complexities.
As between the two fundamental operations that may be performed on a storage bit (a “write” or a “read”), the write operation is generally more complex. With respect to traditional cross-point memory arrays, while the magnetic field of the data layer 101 of a desired cell may be altered, it is desirable not to adversely affect or alter the data layers 101 of neighboring cells. Write operations generally require greater electrical current and magnetic fields, requiring more robust characteristics in the power supply, row and column conductors and appropriate buffering space. Therefore, design and manufacturing issues are generally focused upon the requirements imposed by the write operation.
With respect to magnetic memory components, it is well known that as size decreases coercivity increases. A large coercivity is generally undesirable, as it requires a greater magnetic field to be switched, which in turn requires a greater power source and potentially larger switching transistors. Providing large power sources and large switching transistors is generally at odds with the focus of nanotechnology to reduce the necessary size of components. In addition, to mitigate the potential of inadvertently switching a neighboring memory cell, nanometer scaled memory cells are generally more widely spaced relative to their overall size than are non-nanometer sized memory cells. Moreover, as the size of the magnetic memory decreases, the unused space between individual memory cells tends to increase.
These issues and current design of the magnetic memory cells also carry over into the design and use of magnetic field sensors such as those commonly used in hard drive read cells and read heads. In such implementation, the data layer 101 is termed a sense layer and is oriented by the magnetic field emanating from a storage bit proximate to the read head. As two-end involvement is present, weakened or degraded data storage bits on the hard drive may not have a sufficient field to properly orient the sense layer.
Hence, in a typical MRAM array a significant amount of overall space may be used simply to provide a physical buffer between the cells. Absent this buffering space, or otherwise reducing it's ratio, a greater volume of storage in the same physical space could be obtained.
Hence, there is a need for an ultra-high density thermally assisted memory array which overcomes one or more of the drawbacks identified above. The present invention satisfies one or more of these needs.